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Optimized Infrastructure
Inferencing

Author:

Gangwon Jo

CEO
Moreh

Gangwon Jo is the co-founder and CEO of Moreh Inc., a startup funded by AMD that develops optimized infrastructure software, enabling more efficient and flexible AI infrastructure at scale. Moreh’s software supports AI workloads on AMD as well as other accelerator platforms, such as Tenstorrent.

Gangwon was the chief architect of “Chundoong,” a supercomputer built using AMD consumer GPUs, which was recognized as one of the world’s TOP500 supercomputers in 2012.

In 2022, Gangwon was named one of MIT Technology Review’s “Innovators Under 35.” He holds a Ph.D. in Electrical and Computer Engineering from Seoul National University.

Gangwon Jo

CEO
Moreh

Gangwon Jo is the co-founder and CEO of Moreh Inc., a startup funded by AMD that develops optimized infrastructure software, enabling more efficient and flexible AI infrastructure at scale. Moreh’s software supports AI workloads on AMD as well as other accelerator platforms, such as Tenstorrent.

Gangwon was the chief architect of “Chundoong,” a supercomputer built using AMD consumer GPUs, which was recognized as one of the world’s TOP500 supercomputers in 2012.

In 2022, Gangwon was named one of MIT Technology Review’s “Innovators Under 35.” He holds a Ph.D. in Electrical and Computer Engineering from Seoul National University.

 

George Song

Principal
Strand Equity

George Song

Principal
Strand Equity

George Song

Principal
Strand Equity
 

Gaurav Shah

VP of Business Development
NeuReality

Gaurav Shah

VP of Business Development
NeuReality

Gaurav Shah

VP of Business Development
NeuReality
 

Paul Piezzo

Enterprise Sales Director
NeuReality

Paul Piezzo

Enterprise Sales Director
NeuReality

Paul Piezzo

Enterprise Sales Director
NeuReality
 

Naveh Grofi

Customer Success Engineer
NeuReality

Naveh Grofi

Customer Success Engineer
NeuReality

Naveh Grofi

Customer Success Engineer
NeuReality
 

Tina Bou-Saba

Founder
CXT Investments

Tina Bou-Saba

Founder
CXT Investments

Tina Bou-Saba

Founder
CXT Investments
 

Richard Henry

Partner
Sandbridge Capital

Richard Henry

Partner
Sandbridge Capital

Richard Henry

Partner
Sandbridge Capital
 

Sam Pritzker

Principal
TSG Consumer

Sam Pritzker

Principal
TSG Consumer

Sam Pritzker

Principal
TSG Consumer

In the new era of AI infrastructure, CMOS scaling remains the workhorse for heavy computational workloads. But the need for an energy-efficient solution imposes a paradigm shift at the interconnect level, requiring an intimate 3D co-integration of advanced ASICs and optical connectivity. 

As the architectural complexity of new products increases, relying on state-of-the-art platforms, with a short path to manufacturing. In this workshop, we will highlight how you can access following technologies for your future products:  

  • Advanced-node ASIC down to TSMC N2 
  • Imec’s integrated photonics platforms from 200G up to co-packaged optics 
  • Imec’s advanced 3D packaging technique from interposer to hybrid bonding 

Location: Room 207

Duration: 1 hour

Author:

Philippe Soussan

Technology Portfolio Director
IMEC

Philippe Soussan is Technology Portfolio Director at imec. For 20 years, he has held different positions in R&D management at imec in the field of sensors, photonics, and 3D packaging. Addressing these technologies from R&D up to manufacturing levels.  

His expertise lies in wafer-scale technologies, and he has authored over 100 publications and holds more than 20 patents in these fields. 

Since 2024, Philippe has been in charge of strategy definition within the “IC-link by imec” sector. This imec business line provides access to design and manufacturing services in the most advanced ASIC and specialty technologies.  

Philippe Soussan

Technology Portfolio Director
IMEC

Philippe Soussan is Technology Portfolio Director at imec. For 20 years, he has held different positions in R&D management at imec in the field of sensors, photonics, and 3D packaging. Addressing these technologies from R&D up to manufacturing levels.  

His expertise lies in wafer-scale technologies, and he has authored over 100 publications and holds more than 20 patents in these fields. 

Since 2024, Philippe has been in charge of strategy definition within the “IC-link by imec” sector. This imec business line provides access to design and manufacturing services in the most advanced ASIC and specialty technologies.